Overall

Objective

This laboratory project focused on designing, simulating, and implementing digital circuits on the Altera DE1-SoC FPGA board using Verilog HDL. The lab combined combinational logic design with sequential logic elements, strengthening both logic minimization skills and hardware description practice.

• Gain experience with Karnaugh Maps (K-maps) to derive minimal-cost Boolean equations.
• Design and test seven-segment display controllers for both numeric and alphabetic outputs.
• D
• Construct and simulate sequential elements such as D flip-flops and multi-bit registers.

Demo Video

https://youtube.com/shorts/KFkuywJB_SI?feature=share

Applied Tool & Methods

• Software: Quartus Prime (for synthesis, simulation, and FPGA programming).

• Hardware: Altera DE1-SoC development board with Cyclone V FPGA, on-board seven-segment displays, switches, pushbuttons, and LEDs.

• Design Process:

  • Logic equations derived with K-maps.
  • Circuits written in Verilog (structural/behavioral).
  • Verified via functional simulation, then deployed to FPGA for live demo.

  Learning Outcomes

  • Developed strong proficiency in logic simplification and Verilog coding.
  • Applied modular design principles by separating circuits into reusable submodules.
  • Gained hands-on experience in FPGA-based hardware implementation.
  • Bridged theory (K-maps, Boolean algebra) with practice (FPGA design flow).

K Map Display

Lab 2-Notes-ver2 (1).pdf

Applied Skill

Verilog